1. Field of Invention
This invention relates to the merging of integrated circuit design data from a custom design flow and from a synthesized digital design flow. Many steps are in the design flow for an integrated circuit. This invention facilitates the place and route step.
2. Description of Related Art
Designing a mixed-signal integrated circuits (IC) requires a complex design flow. At the center of the flow is the place and route (P&R) step where the layout of the IC is generated. From layout, a straightforward series of steps can be taken to move the IC into manufacturing. Prior to the P&R step, several teams are involved in generating the data required for P&R. There are two primary sources of data. There are data from a custom design flow. This data primarily consist of geometric, constraint, and parameterized cell information. Custom design data includes information on the placement and floorplanning of Intellectual Property (IP) blocks, pre-routing information on power and analog wires, and placement information of guard rings. This data is typically encoded in a database. There are also data from the system teams who write data for an automated synthesized digital design flow. This data primarily consists of full connectivity data, standard cell, and timing information. The connectivity data often begins in text formats and is encoded into the database using an automated tool. To complete P&R, data from these two sources must be merged at the database level into a consistent representation that the P&R tools understand. Further, as the design process continues and as the design data input changes, the merged data must be incrementally updated. An engineering change order (ECO) defines a requirement that changes the design data input.
The traditional approach to completing the layout for the IC is not to have a single merge step, but a series of translations, targeted to allow individual tools in the flow to operate. The translators include manual copy and paste operations and the use of targeted translators that operate on the text formats. These targeted translators typically translate only sufficient information to allow a particular tool to operate. The translations are typically incomplete. As a result, many translations have to occur to complete the flow. As ECOs occur throughout the design process, these translators are continually run. The end result is a process that is error prone, time consuming, and one that results in data loss.